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  • re: Fixing the Query Optimizer Cost Model

    hello Glenn, that is correct, I endorse single socket with the Xeon E5 v4 processor that is capable of 2-way. You could buy either a UP or DP motherboard from Supermicro with 1-socket populated. Or you could buy a Dell or HP server with 1 E5v4. Of course the E3 is not chump change, 16 PCI-E lanes is workable if I could get 4 x4 + the DMI equiv ...
    Posted to Joe Chang (Weblog) by jchang on February 21, 2017
  • Fixing the Query Optimizer Cost Model

    The model for the cost of operations used by the SQL Server query optimizer to produce an execution plan is rather simple. It has been largely unchanged since SQL Server version 7, RTM in 1998. Back then, SQL Server had not yet achieved tier 1 status with commensurate development resources. Some adjustments were made in version ...
    Posted to Joe Chang (Weblog) by jchang on February 20, 2017
  • re: Parallel Execution on SQL Server 2016

    The key to Hyper-Threading is in there being significant round-trip memory access no-op cycles. For transactions, this is very true. In other posts, I have suggested that this might be around 5% of instructions, meaning that perhaps only 12% of cycles are actually used by a thread. Hence scaling with HT is almost linear in the absence of ...
    Posted to Joe Chang (Weblog) by jchang on February 5, 2017
  • re: Parallel Execution on SQL Server 2016

    In principle, Azure, AWS etc. are good options to have. Very few companies have the resources to hyper-optimize IT infrastructure administration. Some &nbsp;have fallen into the trap of gold-bricking, using &quot;enterprise&quot; SANs, i.e. about $6K per HDD. Other have become obstructors of IT. The problem is that every time something good comes ...
    Posted to Joe Chang (Weblog) by jchang on February 5, 2017
  • Parallel Execution on SQL Server 2016

    There are a number of interesting questions in parallel execution performance that can be investigated using the TPC-H kit, which has a data generator. There are also supplemental files that accompany published results. Important questions in parallel execution are: scaling versus degree of parallelism (DOP) on physical cores, ...
    Posted to Joe Chang (Weblog) by jchang on February 1, 2017
  • re: Saving a Few Lines of Code by Performing Multiple Operations in a Single Command

    change the order to DROP TABLE dbo.Table2, dbo.Table1 to avoid the foreign key constraint
    Posted to Louis Davidson (Weblog) by jchang on January 23, 2017
  • Rethinking System Architecture

    Server system memory capacities have grown to ridiculously large levels far beyond what is necessary now that solid-state storage is practical. Why is this a problem? Because the requirement that memory capacity trumps other criteria has driven system architecture to be focused exclusively on low cost DRAM. DDR DRAM, currently in its ...
    Posted to Joe Chang (Weblog) by jchang on January 10, 2017
  • Intel Processor Architecture 2020

    There is an article on WCCFtech, that a new Intel processor architecture to succeed the lake processors (Sky, Cannon, Ice and Tiger) will be ''faster and leaner'' and more interestingly might not be entirely compatible with older software. The original source is bitsandchips.it. I suppose it is curious that the Lake processors form a ...
    Posted to Joe Chang (Weblog) by jchang on December 27, 2016
  • Memory Latency and NUMA

    It should be intuitively obvious that round-trip memory access latency is one of the most important factors in modern server system architecture for transaction processing databases. Yet this is a topic that no one talks about. Vendors do not want to discuss this because no near or long-term actions are planned. Outsiders cannot write a ...
    Posted to Joe Chang (Weblog) by jchang on December 18, 2016
  • re: SQL Server 2016 SP1 shocks the world!!!

    almost 20 years ago, when Intel was doing the SSE vector floating point in what became Pentium III, there was some thought that this was an important feature that required 2M transistors back when 2M transistors was a lot (PII was 7.5M, Katmai PIII 9.5M), it ought to get a premium over same frequency PII. However, the reality was that software ...
    Posted to Damian Widera (Weblog) by jchang on November 18, 2016
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